View AD9753_885860.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 rev. pra preliminary technical data features 12-bit dual muxed port dac 300 msps output update rate excellent sfdr and imd: 75 db internal 2x clock doubler/pll differential or single ended clock input on-chip 1.2 v reference single +3 v supply operation power dissipation: <300 mw @ 3v power down mode: 25 mw avdd @ 3 v 48-lead lqfp applications communications: lmds, lmcs, mmds basestations digital synthesis quadrature modulation product description the AD9753 is a dual muxed port, ultra high-speed, single channel,12-bit cmos dac. it integrates a high-quality 12-bit txdac+ tm core, a voltage refer- ence, and digital interface circuitry into a small 48-lead lqfp package. the AD9753 offers exceptional ac and dc performance while supporting update rates up to 300msps. the AD9753 has been optimized for ultra high speed applications up to 300msps where data rates exceed those possible on a single data interface port dac. the digital interface consists of two buffered latches as well as control logic. these latches are time multiplexed to the high speed dac. the internal pll drives the dac latch at twice the speed of the exter- nally applied clock and is thus able to interleave the data from the two input channels to the dac. the resulting output data rate is then twice that of the two input channels. for applications that are sensitive to clock jitter, the internal 2 pll clock multiplier can be disabled by connecting the pll power supply pin (pllvdd) to ground. in pll disable mode, a 2 clock must be supplied and is divided by two internally. the clk inputs (clk+/clk-) can be driven either differentially or single ended, with a signal swing as low as 1v pk-pk. the dac utilizes a segmented current source architec- a 12-bit, 300 msps high speed txdac+ ? ? ? ? ? d/a converter AD9753* preliminary technical data 7-1-99 block diagram information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. differential current outputs support single-ended or differential applications. the differential outputs each provide a nominal full-scale current from 2 to 20ma. the AD9753 is manufactured on an advanced low cost 0.35 m m cmos process. it operates from a single supply of 2.7 v to 3.6 v and consumes <300 mw of power. product highlights 1. the AD9753 is a member of a pin-compatible family of high speed txdac+s providing 10, 12, and 14 bit resolution. 2. ultra high speed 300msps conversion rate. 3. dual 12-bit latched multiplexed input ports: the AD9753 features a flexible dual-port interface allowing high speed data interfacing. 4. internal pll clock doubler, differential and single ended clock inputs. 5. low power: complete cmos dac function operates on <300 mw from a 2.7 v to 3.6 v single supply. the dac full-scale current can be reduced for lower power operation. 6. on-chip voltage reference: the AD9753 includes a 1.20 v temperature-compensated bandgap voltage reference. one technology way, p .o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 txdac+ is a trademark of analog devices, inc. *patent pending dac reference AD9753 dvdd dcom avdd acom iouta ioutb refio fsadj lpf reset lock port1 port2 clk+ clk- clkvdd pllvdd clkcom pll clock multiplier latch latch dac latch mux div0 div1
preliminary technical data 2 rev. pra dc specifications (tmin to tmax , avdd = +3 v, dvdd = +3 v, plvdd=3v, clkvdd=3 v, ioutfs = 20 ma, unless otherwise noted) parameter min typ max units resolution 12 bits dc accuracy 1 integral linearity error (inl) -1.5 0.5 1.5 lsb differential nonlinearity (dnl) -0.5 0.25 0.5 lsb analog output offset error C0.025 +0.025 % of fsr gain error (without internal reference) C10 2 +10 % of fsr gain error (with internal reference) C10 1 +10 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range C1.0 1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.08 1.20 1.32 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m w temperature coefficients offset drift 0 ppm of fsr/c gain drift (without internal reference) 50 ppm of fsr/c gain drift (with internal reference) 100 ppm of fsr/c reference voltage drift 50 ppm/c power supply supply voltages a vdd 2.7 3.0 3.3 v dvdd 2.7 3.0 3.3 v pllvdd 2.7 3.0 3.3 v clkvdd 2.7 3.0 3.3 v analog supply current (iavdd) 3 3 ma digital supply current (idvdd) 6 5 ma power dissipation (3 v, ioutfs = 20 ma) 300 m w power supply rejection ratio 4 avdd C0.4 +0.4 % of fsr/v power supply rejection ratio 4 dvdd C0.05 +0.05 % of fsr/v operating range C40 +85 c notes 1 measured at iouta, driving a virtual ground. 2 nominal full-scale current, ioutfs, is 32 the iref current. 3 an external buffer amplifier is recommended to drive any external load. 4 5% power supply variation. specifications subject to change without notice. AD9753
3 rev. pra preliminary technical data dynamic specifications (tmin to tmax, avdd = +3 v, dvdd = +3 v, clkvdd = 3 v, pllvdd = 0v, ioutfs = 20 ma, differential transformer coupled output, 50 w w w w w doubly terminated, unless otherwise noted) parameter min typ max units dynamic performance maximum output update rate (f clock ) 300 msps output settling time (t st ) (to 0.1%) 5 35 ns output propagation delay (t pd ) 5 1ns glitch impulse 5 5 pv-s output rise time (10% to 90%) 5 2.5 ns output fall time (10% to 90%) 5 2.5 ns output noise (ioutfs = 20 ma) 5 0 pa/ ? hz output noise (ioutfs = 2 ma) 3 0 pa/ ? hz ac linearity spurious-free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz 0 dbfs output ta = +25c 7 8 8 3 dbc tmin to tmax 7 4 dbc C6 dbfs output 7 9 dbc C12 dbfs output 7 9 dbc C18 dbfs output 7 2 dbc f clock = 50 msps; f out = 1.00 mhz 8 1 dbc f clock = 50 msps; f out = 2.51 mhz 7 9 dbc f clock = 50 msps; f out = 5.02 mhz 7 8 dbc f clock = 50 msps; f out = 14.02 mhz 6 8 dbc f clock = 50 msps; f out = 20.2 mhz 6 2 dbc spurious-free dynamic range within a window f clock = 25 msps; f out =1.00 mhz; 2 mhz span ta = +25c 7 8 8 8 dbc tmin to tmax 7 6 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 8 6 dbc f clock = 150 msps; f out = 5.04 mhz; 4 mhz span 8 4 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz ta = +25c C81 C76 dbc tmin to tmax C74 dbc f clock = 50 mhz; f out = 2.00 mhz C78 dbc f clock = 150 mhz; f out = 2.00 mhz C78 dbc notes 5 measured single-ended into 50 w load. specifications subject to change without notice. AD9753
preliminary technical data 4 rev. pra digital specifications (tmin to tmax, avdd = +3 v, dvdd = +3 v, clkvdd = 3 v, pllvdd = 3 v, ioutfs = 20 ma, unless otherwise noted) parameter min typ max units digital inputs 6 logic 1 2.1 3 v logic 0 0 0.9 v logic 1 current C10 +10 a logic 0 current C10 +10 a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) tbd ns min clk freq 7 6.25 mhz absolute maximum ratings* with parameter respect to min max units avdd acom C0.3 +3.9 v dvdd dcom C0.3 +3.9 v plvdd dcom C0.3 +3.9 v clkvdd dcom C0.3 +3.9 v acom dcom C0.3 +0.3 v avdd dvdd C6.5 +3.9 v clock dcom C0.3 dvdd + 0.3 v digital inputs dcom C0.3 dvdd + 0.3 v iouta, ioutb acom C1.0 a vdd + 0.3 v comp1 acom C0.3 a vdd + 0.3 v refio, fsadj acom C0.3 a vdd + 0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide model t emperature package package range description options AD9753ast C40c to +85c 48-lead lqfp st-48 AD9753-eb evaluation board notes 6 div0,div1=(1,1). 7 min clk freq only applies when using internal pll. when pll is disabled, there is no minimum clk frequency. figure 1. dac i/o timing AD9753 data in port 2 data y clkin (pll active) 1 clock (pll disabled) t lpw t pd 1/2 cycle + t pd iouta or ioutb data y data x data in port 1 t s t h data x thermal characteristics thermal resistance 48-lead lqfp q ja = 91c/w
5 rev. pra preliminary technical data pin function descriptions pin no. name description 43 iouta differential dac current output 42 ioutb differential dac current output 39 refio reference input/output 37,38 div0,div1 control inputs for pll and input port selector mode, see tables i and ii for details 40 fsadj full-scale current output adjust 41 avdd analog supply voltage 44 acom analog common 6,21 dvdd digital supply voltage 5,22 dcom digital common 47 pllvdd phase locked loop supply voltage 48 clkvdd clock supply voltage 45 clkcom clock and phase locked loop common 3 clk+ differential clock input 4 clk- differential clock input 46 lpf pll low pass filter 1 reset internal clock divider reset 2 lock pll lock indicator output 7-18 db11-p1/db0-p1 data bits db11 to db0, port 1 23-34 db11-p2/db0-p2 data bits db11 to db0, port 2 AD9753 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 AD9753 300 msps dual port dac top view 48 pin lqfp p1b5 p1b7 p1b6 reset lock clk+ clk- dcom dvdd msb-p1b11 p1b10 dcom dvdd reserved reserved lsb-p1b0 p1b8 p1b9 reserved lsb-p2b0 msb-p2b11 p2b10 p2b9 p2b8 p2b7 p2b6 p2b5 p2b4 p2b3 p2b2 clkvdd pllvdd lpf clkcom acom iouta ioutb avdd fsadj refio div1 div0 p2b1 reserved p1b4 p1b2 p1b1 p1b3 reserved = no user connections
preliminary technical data 6 rev. pra functional description figure 2 shows a simplified block diagram of the AD9753. the AD9753 consists of a pmos current source array capable of providing up to 20ma of full- scale current, i outfs . the array is divided into 31 equal sources that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are a binary weighted fraction of the middle bit current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances dynamic performance for multitone or low amplitude signals and helps maintain the dacs high output impedance (i.e., >100k w ). AD9753 all of the current sources are switched to one or the other of the two outputs (i.e., iouta or ioutb) via pmos differential current switches. the switches are based on a new architecture that drastically improves distortion performance. this new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the AD9753 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 2.7 volt to 3.6 volt range. the digital section, which is capable of operating at a 300 msps clock rate, consists of edge- triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v bandgap voltage reference and a reference control amplifier. the full-scale output current is regulated by the reference control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the refer- ence current i ref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is thirty-two times the value of i ref . reference operation the AD9753 contains an internal 1.20 v bandgap reference. this can be easily overdriven by an external reference with no effect on performance. refio serves as either an input or output depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 m f capacitor. the internal reference voltage will be present at refio. if the voltage at refio is to be used elsewhere in the circuit, an external buffer amplifier with an input bias current less than 100na should be used. an example of the use of the internal reference is given in figure 3. an external reference can be applied to refio as shown in figure 4. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal reference is overdriven, and the relatively high input impedance of refio minimizes any loading of the external refer- ence. reference control amplifier the AD9753 also contains an internal control ampli- fier that is used to regulate the dacs full-scale output current, i outfs . the control amplifier is configured as a voltage to current converter as shown in figure 3, so that its current output, i ref , is determined by the ratio of v refio and an external resistor, r set , as stated in equation 4. i ref is applied to the segmented current sources with the proper scaling factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting iref between 62.5 a and 625 a. the wide adjust- ment span of i outfs provides several application figure 2. simplified block diagram iouta ioutb segmented switches for db0 to db11 dac avdd acom port 1 latch port 2 latch 2-1 mux dac latch pmos current source array 1.2v ref + - refio fsadj dcom dvdd pll circuitry clk+ pllvdd clkvdd clkcom lpf lock reset clk- r set 2k w +2.7 to +3.6v 0.1 m f rload 50 w rload 50 w vouta voutb vdiff=vouta-voutb db0-db11 db0-db11 digital data inputs AD9753 div0 div1
7 rev. pra preliminary technical data AD9753 benefits. the first benefit relates directly to the power dissipation of the AD9753, which is proportional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500khz and can be used for low frequency small signal multiplying applica- tions. pll clock multiplier operation the phase locked loop (pll) is intrinsic to the operation of the AD9753 in that it produces the necessary internally synchronized 2 clock for the edge triggered latches, multiplexer and dac. with pllvdd connected to its supply voltage, the AD9753 is in pll active mode. fig 5 shows a functional block diagram of the AD9753 clock control circuitry with pll active. the circuitry consists of a phase detector, charge pump, voltage controlled oscillator (vco), input data rate range control, clock logic circuitry and control input/outputs. the ? 2 logic in the feedback loop allows the pll to generate the 2 clock needed for the dac output latch. figure 6 defines the input and output timing for the AD9753 with the pll active. clk in figure 6 represents the clock which is generated external to the AD9753 which also updates the input data at ports 1 and 2. clk may be applied as a single ended signal by tying clk- to mid supply and applying clk to clk+, or as a differential signal applied to clk+ and clk-. reset has no purpose when using the internal pll and should be grounded. when the AD9753 is in pll active mode, lock is the output of the internal phase detector. when locked, the lock output in this mode will be a logic 1. typically, the vco can generate outputs of 100 to 400 mhz. the range control is used to keep the vco operating within its designed range, while allowing input clocks as low as 6.25 mhz. with the pll active, logic levels at div0 and div1 determine the divide ratio of the range controller. table i gives the frequency range of the input clock for the different states of div0 and div1. a 392 w resistor and 1.0 m f capacitor connected in series from lpf to pllvdd are required to optimize the phase noise vs. settling/acquisition time character- istics of the pll. to obtain optimum noise and distortion performance, pllvdd should be set to a voltage level similar to dvdd. snr is partly a function of the jitter generated by the clock circuitry. as a result, any noise on pllvdd or clkvdd may decrease the snr at the output of the dac. to minimize this potential problem, pllvdd and clkvdd can be connected to dvdd using an lc filter network similar to that shown in figure 7. dac timing with pll active in pll active mode, port 1 and port 2 input latches are updated on the rising edge of clk. on the same rising edge, data which was previously stored in the input port 2 latch is written to the dac output latch. the dac output will update accordingly after a short propagation delay. following the rising edge, at a time equal to half the period of clk, the data in the port 1 latch will be written to the dac output latch, again with a corre- sponding change in the dac output. on the next rising edge of clk, the cycle begins again with the two input port latches being updated, and the dac output latch being updated with the current data in the port 2 input latch. figure 5. AD9753 clock circuitry with pll active figure 3. internal reference configuration figure 4. external reference configuration optional external reference buffer additional external load 0.1 m f 2k w refio fsadj 1.2v ref avdd current source array AD9753 reference section i ref avdd external reference 2k w refio fsadj 1.2v ref avdd current source array AD9753 reference section i ref clk+ clk- diff to single ended amp to input latches ? 2 phase detector charge pump vco lpf pllvdd +2.7 to +3.6v 392 w 1.0 m f lock range control ( ?1, 2, 4, 8 ) to dac latch div0 div1 clkvdd (+2.7 to +3.6v) clkcom
preliminary technical data 8 rev. pra due to the internal pll, the time at which the data in the port 1 and port 2 input latches is written to the dac latch is independent of the duty cycle of clk. pll disabled mode when pllvdd is grounded, the pll is disabled. an external clock must now drive the clk inputs at the desired dac output update data rate. the speed and timing of the data present at input ports 1 and 2 is now dependent on whether or not the AD9753 is interleav- ing the digital input data, or only responding to data on a single port. figure 8 is a functional block diagram of the AD9753 clock control circuitry with the pll disabled. div0 and div1 no longer control the pll, but are used to set the control on the input mux for either interleaving or non-interleaving the input data. the different modes for states of div0 and div1 are given in table ii. interleaving data with pll disabled the relationship between the internal and external clocks in this mode is shown in figure 9. a clock at the output update data rate (2 the input data rate) must be applied to the clk inputs. the input latches are now updated by the internally generated 1 clock, while the dac latch is updated by the external 2 clock. a delayed version of the 1 clock is available at the lock pin. updates to the data at input ports 1 and 2 should be synchronized to the rising edge of the external 2 clock which corresponds to the risng edge of the 1 internal clock as shown in figure 9. to ensure this synchronization, a logic 1 should be momentarily applied to the reset pin on power up, before clk is applied. AD9753 data in port 2 data y clk t lpw t pd 1/2 cycle + t pd iouta or ioutb data y data x data in port 1 t s t h data x figure 6. dac input timing requirements with pll active figure 6a. figure 7. lc network for power filtering table ii, input mode for div0, div1 levels with pll disabled input mode div1 div0 interleaved 0 0 port 1 0 1 port 2 1 0 not allowed 1 1 table i, clk rates for div0, div1 levels with pll active clk freq div1 div0 range controller 50-150 mhz 0 0 ? ? ? ? ? 1 25-100 mhz 0 1 ? ? ? ? ? 2 12.5-50 mhz 1 0 ? ? ? ? ? 4 6.25-25 mhz 1 1 ? ? ? ? ? 8 figure 8. AD9753 clock circuitry with pll disabled clkin+ clkin- diff to single ended amp to input latches clock logic ( ? 1 or ? 2) pllvdd lock reset to dac latch div0 div1 to internal mux data in port 1 port 2 data w data y iouta or ioutb clk data x data z data w data x data y data z xxx ttl/cmos logic circuits 2.7 to 3.6v power supply ferrite beads pllvdd clkcom 100 m f elect. 10-22 m f tant. 0.1 m f ceramic clkvdd figure 6b.
9 rev. pra preliminary technical data non-interleaved data with pll disabled if the data at only one port is required, no interleaving is done, and the AD9753 interface operates as a typical double buffered latch. on the rising edge of the 1 clock, input latch 1 or 2 is updated with the present input data. on the next rising edge, the dac latch is updated and a propagation time later the dac output reflects this change. figure 10 represents the AD9753 timing in this mode. dac transfer function the AD9753 provides complementary current outputs, iouta and ioutb. iouta will provide a near full- scale current output, i outfs , when all bits are high (i.e., dac code = 4095) while ioutb, the complemen- tary output, provides no current. the current output appearing at iouta and ioutb is a function of both the input code and i outfs and can be expressed as: i outa = ( dac code /4096) i outfs (1) i outb = (4095 C dac code )/4096 i outfs (2) where dac code = 0 to 4095 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note, r load may represent the equivalent load resistance seen by iouta or ioutb as would be the case in a doubly terminated 50 w or 75 w cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply : v outa = i outa r load (5) v outb = i outb r load (6) note the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity perfor- mance. v diff = ( i outa C i outb ) r load (7) substituting the values of i outa , i outb and i ref ; v diff can be expressed as: v diff = {(2 dac code C 4095)/4096} (32 r load / r set ) v refio (8) these last two equations highlight some of the advan- tages of operating the AD9753 differentially. first, the differential operation will help cancel common- mode error sources associated with i outa and i outb such as noise, distortion and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note, that the gain drift temperature performance for a single-ended (v outa and v outb ) or differential output (v diff ) of the AD9753 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship as shown in equation 8. analog outputs the AD9753 produces two complementary current outputs, i outa and i outb , which may be configured for single-ended or differential operation. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer func- tion section by equations 5 through 8. the differ- ential voltage, v diff , existing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. the figure 9. AD9753 timing requirements, interleaving data with pll disabled data y t s t h data x data in port 2 2 clk t lpw t pd data y data x iouta or ioutb data in port 1 delayed 1 clk t pd t d data in port 1 or port 2 t s t h 1 clock t lpw t pd iouta or ioutb data out port 1 or port2 xx figure 10. AD9753 timing requirements, non- interleaved data with pll disabled AD9753
preliminary technical data 10 rev. pra ac performance of the AD9753 is optimum and specified using a differential transformer coupled output in which the voltage swing at iouta and ioutb is limited to 0.5 v. if a single-ended unipo- lar output is desirable, iouta should be selected as the output, with ioutb grounded. the distortion and noise performance of the AD9753 can be enhanced when it is configured for differential operation. the common-mode error sources of both i outa and i outb can be significantly reduced by the common-mode rejection of a transformer or differen- tial amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. this is due to the first order cancellation of various dynamic common- mode distortion mechanisms, digital feedthrough and noise. performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). since the output currents of iouta and ioutb are complementary, they become additive when processed differentially. a properly selected transformer will allow the AD9753 to provide the required power and voltage levels to different loads. refer to applying the AD9753 section for examples of various output configurations. the output impedance of iouta and ioutb is determined by the equivalent parallel combination of the pmos switches associated with the current sources and is typically 100 k w in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining iouta and/or ioutb at a virtual ground via an i-v op amp configuration will result in the optimum dc linearity. note the inl/dnl specifi- cations for the AD9753 are measured with iouta maintained at a virtual ground via an op amp. iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of C1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9753. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. the opti- mum distortion performance for a single-ended or differential output is achieved when the maximum full- scale signal at iouta and ioutb does not exceed 0.5 v. applications requiring the AD9753s output (i.e., v outa and/or v outb ) to extend its output compli- ance range should size r load accordingly. operation beyond this compliance range will adversely affect the AD9753s linearity performance and subsequently degrade its distortion performance. digital inputs the AD9753s digital input consists of two channels of 12 data input pins each and a pair of differential clock input pins. the 12-bit parallel data inputs follow standard straight binary coding where db11 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge- triggered master slave latch. with the pll active, the dac output is updated twice for every input clock period, as shown in figure 6, 9 and 10, and is de- signed to support a clock input rate as high as 150 msps. with the pll active, this gives a dac output update rate of 300msps. the clock can be operated at any duty cycle that meets the specified latch pulse width. the setup and hold times can also be varied within the clock cycle as long as the specified mini- mum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. the digital inputs are cmos-compatible with logic thresholds, vthreshold, set to approximately half the digital positive supply (dvdd) or vthreshold = dvdd/2 (20%) the internal digital circuitry of the AD9753 is capable of operating over a digital supply range of 2.7 v to 3.6 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers voh(max). a dvdd of 3 v to 3.3 v will typically ensure proper compatibility with most ttl logic families. figure 11 shows the equivalent digital input circuit for the data and clock inputs. digital input dvdd figure 11. equivalent digital input AD9753
11 rev. pra preliminary technical data the AD9753 features a flexible differential clock input operatingfrom separate supplies (i.e., clkvdd, clkcom) to achieve optimum jitter performance. the two clock inputs, clk+ and clk-, can be driven from a single-ended or differential clock source. for single ended operation, clk+ should be driven by a logic source while clk- should be set to the threshold voltage of the logic source. this can be done via a resistor divider/capacitor network as shown in figure 12a. for differential operation, both clk+ and clk- should be biased to clkvdd/2 via a resistor divider network as shown in figure 12b. since the output of the AD9753 is capable of being updated at up to 300 msps, the quality of the clock and data input signals are important in achieving the optimum performance. operating the AD9753 with reduced logic swings and a corresponding digital supply (dvdd) will result in the lowest data feedthrough and on-chip digital noise. the drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9753 as well as its required min/max input logic level thresholds. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 w to 100 w ) between the AD9753 digital inputs and driver outputs may be helpful in reducing any over- shooting and ringing at the digital inputs that contrib- ute to data feedthrough. for longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain clean digital inputs. the external clock driver circuitry should provide the AD9753 with a low jitter clock input meeting the min/ max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application. note that the clock input could also be driven via a sine wave, which is centered around the digital thresh- old (i.e., dvdd/2) and meets the min/max logic threshold. this will typically result in a slight degrada- tion in the phase noise, which becomes more notice- able at higher sampling rates and output frequencies. also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and, subse- quently, cut into the required data setup and hold times. figure 12a. single ended clock interface 0.1 m f v threshold clk+ clkvdd clk- clkcom r series 0.1 m f clk+ clkvdd clk- clkcom 0.1 m f 0.1 m f figure 12b. differential clock interface AD9753
preliminary technical data 12 rev. pra 48 pin lqfp package (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0 8 min 0 8 - 7 8 0.006 (0.15) 0.002 (0.05) 0.007 (0.18) 0.004 (0.09) AD9753

▲Up To Search▲

Price & Availability of AD9753

	To Download AD9753 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .